(a) Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a multi-level interconnection structure.
(b) Description of the Related Arts
It is well known that a silicidation technology of a metallic layer is applicable to reduce either a resistivity of a diffused layer itself or a contact resistance between a contact plug and a diffused layer. FIGS. 1A to 1D illustrate cross-sectional views of a first conventional semiconductor device in consecutive steps of forming a metal silicide structure.
The semiconductor device has a P-type silicon substrate 1, a field oxide film 2 and a gate oxide film 3 formed on a main surface of the substrate 1 as shown in FIG. 1A. An N-type dopant is introduced into the main surface of the substrate 1 to form a diffused layer 4. As a metallic layer 6, a titanium film, for instance, is deposited onto the main surface of the substrate 1 from which the gate oxide film 3 has been removed in a self-aligned manner as shown in FIG. 1B. A metal silicide layer 8 is then formed from the metallic layer 6 by a heat treatment on the N-type diffused layer 4 as shown in FIG. 1C. An unreacted titanium residues 6a are removed from the surface of the field oxide film 2 to form a final metal silicide structure as shown in FIG. 1D.
On the other hand, among the devices that employ a metal silicide layer as an interconnection between multilevel interconnection layers, a second conventional semiconductor device having a metal silicide structure formed by a method including a silicidation reaction is described in Publication No. JP-A-91-234062 as shown in FIGS. 2A-2E. An N-type diffused layer 4 is formed on the main surface of a silicon substrate 1 on which a field oxide film 2 and a gate oxide film 3 are formed as shown in FIG. 2A. As a metallic layer 6, a titanium film, for instance, is deposited covering the main surface from which the gate oxide film 3 has been removed in a self-aligned manner as shown in FIG. 2B. A silicon layer 7 is then deposited covering the main surface and selectively removed out of regions other than the area for local interconnection as shown in FIG. 2C. A heat treatment is then carried out to induce a silicidation reaction among the N-type diffused region 4, the metallic layer 6 and the silicon layer 7 to form a metal silicide layer 8 as shown in FIG. 2D. A removal of unreacted titanium residues 6a completes a silicidation step for the diffused layer 4 and a formation of the local interconnection as shown in FIG. 2E.
FIGS. 3A-3E and FIGS. 4A-4E show a third and a fourth conventional semiconductor devices, respectively, in consecutive steps for fabricating contact electrodes and interconnection layers, which are described in Publication No. JP-A-87-34954.
In the third conventional semiconductor device, a field oxide film 2 and a gate oxide film 3 are formed on a P-type silicon substrate 1 as shown in FIG. 3A. An N-type diffused layer 4 is then formed by introduction of donor impurities. As an interlayer insulating film 5, a chemically vapor deposited (CVD) silicon dioxide (SiO.sub.2) film, for instance, is formed, in which a contact-hole 9 (a via-hole used for a first-level interconnection, which will be referred to as a "via-hole" hereinafter) is formed. A metal silicide film 18 such as a titanium silicide film, for instance, is then deposited as shown in FIG. 3B, following which a silicon layer 7 is further deposited as shown in FIG. 3C. An etch-back of the silicon layer 7 is performed to leave a contact plug 7a within the via-hole 9 located on the metal silicide film 18 as shown in FIG. 3D. An etch-removal of the metal silicide film 18 from regions other than interconnection areas completes a final structure of the interconnections as shown in FIG. 3E.
In the fourth conventional semiconductor device as shown in FIGS. 4A to 4E, an N-type diffused layer 4 is formed on a main surface of a P-type silicon substrate 1 on which a field oxide film 2 and a gate oxide film 3 have been formed as shown in FIG. 4A. An interlayer insulating film 5 such as a CVD-SiO.sub.2 film is also deposited, through which a via-hole 9 is formed. A metallic layer 6 such as a titanium film is then deposited as shown in FIG. 4B, following which a silicon layer 7 is deposited as shown in FIG. 4C. An etch-back of the silicon layer 7 is performed to leave a contact electrode in the via-hole 9 located on the metallic layer 6 as shown in FIG. 4D. An etch-removal of the metallic layer 6 from regions other than interconnection areas provides a final interconnection structure as shown in FIG. 4E.
The interconnection structures illustrated in FIGS. 3A-3E and FIGS. 4A-4E include a contact electrode electrically connecting an N-type diffused layer 4 with interconnection layers deposited on an interlayer insulating film 5 using either a metallic layer 6 or a metal silicide layer 18 located on the bottom surface and on the sidewall surface of a via-hole 9. However, those conventional device structures have problems which are described later.